Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code


출처: http://www.edn.com/design/integrated-circuit-design/4437919/Product-how-to–Achieving-STARC-and-DO-254-compliance-using-HDL-Coder-generated-code

 

HDL용 coding guideline이 존재한다. 없을거라고 생각하진 않았지만,

STARC DSG VHDL Rules
STARC DSG Verilog Rules

Model based development에서 c용 source code가 생성되는 것뿐만 아니라 HDL code가 생성되다 보니까 c 스타일의 개발과 유사하게 흘러가는 듯하다. low level의 source code라는 점에서는 크게 다를바는 없다고 생각한다. detail하게 들어가면 달라질 수 있겠지만,,

 

전체적으로는 Mathworks의 HDL development 프로세스를 지원하는 도구의 활용 방안을 설명해 놓은 article이라고 볼 수 있겠다.

HDL용 Coding guideline이 있다는 정보를 get함

 

Some of the RTL coding standards that HDL Coder generated code is built on:

  • DO-254: The DO-254 standard was formally recognized by the FAA in 2005 via AC 20-152 as a means of compliance for the design of complex electronic hardware in airborne systems. Complex electronic hardware includes devices like Field Programmable Gate Arrays (FPGA), Programmable Logic Devices (PLD), and Application Specific Integrated Circuits (ASIC).
  • STARC: Semiconductor Technology Academic Research Center (STARC) policy guidelines are an extensive set of rules that ASIC and system on chip (SoC) designers use to perform in-depth structural analysis on Verilog and VHDL Register Transfer Level (RTL) descriptions. STARC guidelines are compiled by consortium of 11 major Japanese semiconductor companies that promote a design standard for IP trade and reuse.
  • RMM: The Reuse Methodology Manual (RMM), 3rd Edition, (ISBN 1-4020-7141-8), outlines a set of best practices for creating reusable designs for use in SoCs.

 

 

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